1. Introduction

   The micro-architecture is a processor, the MCU core, that implements an specific architecture. It may also add some other features and components, such as an interrupt controller, a memory protecture unit (MPU), external bus interfaces.

   For example, the Cortex-M3 processor (STM32F10x core) implements the on ARMv7-M architecture. Based on ARMv7-M, it defines #pipeline, . Moreover, it also has a nested vectored interrupt controller (NVIC), a MPU, a couple of bus interface.

   

2. Cortex-M3 configuration and components

   1. Programming Mode

      It support two operating modes. The operating mode is different from the privileged and unprivileged mode. In the thread mode, code can be executed as privileged or unprivileged. So the [un]privileged is under the thread mode. It also has two stacks that are pointed by two stack pointer registers, main stack and process stack. But the two registers are banked register, which means they has the same address.

      • Thread mode: entered on Reset, and can be entered as a result of an exception return. (code is under either privileged or unprivileged execution)
      • Handler mode: entered as a result of an exception. (code is under privilege execution, which means all instructions can be used)
      • Main stack: after reset all code (main and handler) uses this main stack.
      • Process stack: after reture from an handler with a special EXC_RETURN value, the main program will use the process stack.

      * The privileged thread mode that use main stack is similar to run a program in a MCU that does not have these features, e.g. Atmega328p.

      

      

      

      User thread mode accesses the "system control space" and special registers except APSR will trigger a fault exception.

      Use as a microcontroller without considering those modes

      

      Term

      • Banked register: multiple registers that have the same address. Using which register is determined by current suition. For example, UART data register is actually two registers that are banked together. The read/write operation refer same address but different physical registers.

   2. Cortex-M3 16 Registers

      1. R0-R7 (8 32-bit registers): general purpose low registers can be accessed by all 16-bit Thumb instructions.
      2. R8-R12 (5 32-bit registers): general purpose high registers. Only 32-bit thumb-2 instruction do not have the ability to access these registers (too short to encode).
      3. R13/SP (MSP & PSP): banked main stack pointer and process stack pointer. When using rR13 to access, only one is visible to program at any time.
         Inside program code, both the MSP and the PSP can be called R13/SP. However, you can access a particular one using special register access instructions (MRS/MSR)
         Using MSR (move general register to special) and MRS (move special to general) instructions, the MSP and PSP can be selected.
         MSP is the default SP. 8-bit microcontroller only has this sp.
         SP's low 2-bit is always 0 (it is hardwired to 0), which means it aligns to word (32-bit) size. The push and pop is -4 or +4.
         
      4. R14/LR linked register: store the return address when invoking a function
         Never seen before: instructions BL and BX (branch with link) is in the sense between call/ret and branch.
         It does not push the return address (PC) to stack or pop the return address from stack to PC, but it may pre-set arguments to registers. It store the return address into the LR.
         PC's LSB is always 0 because 16-bit instruction, but the LR's LSB is read/writable instead of hard wired.
      5. R15/PC: program counter
         LSB of PC: align to half-word so it is always 0. So reading always results in 0, but writing the LSB 1 indicates using Thumb, 0 indicates ARM instruction. Because cortex-M3 does not support ARM instruction, it would result in a fault exception.
         Reading PC: due to pipeline, the code is prefetched to ALU, and then PC + 2 or 4, then implement. Therefore, the code address is different from the read PC by 4. Only 32-bit thumb-2 can access it.
         Writing PC: it cause branching and the LSB must be 1 to indicate this is a Thumb instruction.

      Special registers

      Special registers do not have address, which means they cannot be accessed through MOV. They can only be accessed with MSR/MRS instructions.

          MRS <reg>, <special_reg>; Read special register
          MSR <special_reg>, <reg>; write to special register
      

      1. xPSR (program status registers)

         [1]APSR (Application Program Status Register)
         [2]IPSR (Interrupt Program Status Register)
         [3]EPSR (Execution Program Status Register)
         

         

         The 3 registers can be access individually, or together by one instruction. When accessing together, the register name is PSR.

             MRS r0, APSR; Read special register
             MSR APSR, r0; write to special register
             ;;
             MRS r0, PSR ; Read the combined program status word
             MSR PSR, r0 ; Write combined program state word
         

         

      2. PRIMASK, FAULTMASK, BASEPRI: control the mask of interrupt

         exception includes software exceptions and hardware interrupts.

         [1]PRIMASK
         1-bit register. = 1 will only allow NMI (nonmaskable interrupt) and the hard fault exception.
         [2]FAULTMASK
         1-bit register. = 1 will only allow NMI.
         [3]BASEPRI (up to 8 bits depending on the vendor supported #priority level)
         It can disable all the interrupts of the same or lower level (lager priority value)

      3. CONTROL: control the operating mode, stack pointer selection

         A 2-bit register
         control[1] = 1 indicates PSP, = 0 indicates MSP.
         control[0] = 1 user statue in thread mode, = 0 privileged in thread mode. (* hanlder mode is always privileged)

         Writing control register is only allowed in the privileged thread mode. In this mode, the CPU can return to user thread mode.

         * From kernel mode to user mode is done by the kernel. From user mode to kernel mode is done by exceptions.

   3. Cortex-M3 execption model

      Cortex-M3 defines a number of system exceptions and interrupts. These part are same between different vendors. The rest of interrupt source is defined by vendors.

      

      

      Vector table provides the initial value of SP and the starting addresses of each exception. After reset, the vector table is alway starting from 0x00 but it is relocatable at the runtime by modifying the NVIC's registers.

      * The LSB of each vector address is always 1 to indicate the exception is to be executed in the Thumb state.

      NVIC (Nested Vectored Interrupt controller)

      The NVIC control interrupt and exception (software?), it can support 240 interrupt source and 256 level of priority

      Who did what?

      [2]

   4. Stack model

      SP is points to the current top (SP decrements 4 before storing)

      Little endian

      

      Two SP may used (MSP in handler mode, PSP in thread mode), then they are pointing to different region.

   5. Reset sequence

      When the process reset, processor reads two words 1). addr 0x00000000 to set SP, 2). addr 0x00000004 reset vector.

      * previous ARM is just like AVR, the vector table is a jmp addr instruction. But now, it is just the pure address.

3. References

   1. Cortex-M3 Technical Reference Manual
   2. The definitive guide to the ARM cortex-M3, 2nd edition