1. Introduction

   The Architecture of a processor defines the instruction set, #registers and functions, memory model, whether having hardware mulitplication and division, whether supporting cache, MPU, TCM.

2. ARMv7-M

   1. Instruction set: only support Thumb instruction with Thumb-2 technology. (No ARM instruction set)
   2. Register:

      ARM-core register:

      • 13 * 32-bit general-purpose registers (R0-R12)
      • 2 SP stack pointers
      • LR link register
      • PC program counter
      • status register
      • mask registers: managing the prioritization scheme for exceptions and interrupts
      • control register (CONTROL): identify the current stack and thread mode privilege level.

      Application Program Status Register:

      • APSR
   3. privilege mode: Privileged/unprivileged execution (e.g. mode bit)
   4. operation mode: Thread/hanlder mode. Thread mode:
   5. Memory mode: A memory mapped architecture. Memory-Mapped architecture: the same address space maps to ROM, registers, RAM, and peripheral I/O

   Hierachical manner

   Different from most of 8-bit microcontroller, like atmega 328p, ARMv7-M is more complicated and sophisticated. The hardware of ARMv7-M has two operating level, application level and system level. The concept of level is directly support by hardware instead of virtual levels provided by software. The distinction between application level and system level is the access of instruction and memory. Because of this, the programming can also be divided into two different levels.

3. System level programming

   1. Memory

      ARMv7-M is a memory mapped architecture. The address space ranges from 0x00000000 to 0xffffffff (2^32 4GB). The whole space is paritioned as 8 * 0.5GB paritions. The address space 0xE0000000 to 0xFFFFFFFF (2^29 512MB) is reserved for system level use.

      * Atmega328p is a independent memory layout that flash, SRAM and EEPROM have independent address space.

      To protected application level code to access privileged range, a MPU is required. The ARMv7-M define a Protected Memory System Architecture (PMSAv7) to do that, but it is optional.

      Endian:

      SCS (System control space)

      This region is a system configuration region.

      1. CPU ID registers
      2. General control and configuration (including the vector table base address)
      3. System handler support (for system interrupts and exceptions)
      4. A SysTick system timer
      5. A Nested Vectored Interrupt Controller (NVIC), supporting up to 496 discrete external interrupts. All exceptions and interrupts share a common prioritization model
      6. Fault status and control registers
      7. The Protected Memory System Architecture (PMSAv7), the MPU is optional when implementing the ARMv7-M
      8. Processor debug

      Memory Maps

      

   2. Exception

      Interrupt is one type of exception

4. Application level programming

5. References

   1. ARMv7-M architecture reference manual
   2. Execution mode